1. Field of the Invention
The present invention relates to a CR oscillation circuit, and particularly to a CR oscillation circuit for controlling an oscillation frequency by an outside resistor.
This application is a counterpart of Japanese Patent Application, Serial Number 086155/2002, filed on Mar. 26, 2002, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
FIGS. 2(A) and 2(B) are respectively diagrams for describing a conventional outside resistor type CR oscillation circuit. FIG. 2(A) is a diagram showing a circuit configuration of the conventional CR oscillation circuit, and FIG. 2(B) is a diagram illustrating operation waveforms.
As shown in FIG. 2(A), the CR oscillation circuit has inverters 201, 202 and 203 connected in series between a node N1 and a node N3. A capacitor 204 is electrically connected both the node N1 and a node N2. The node N2 is electrically connected both the inverter 202 and the inverter 203. The node N1 is electrically connected to a terminal 205 for connecting one end of an outside resistor R1. The node N3 on the output side of the inverter 203 is electrically connected to a terminal 206 for connecting the other end of the outside resistor R1. An oscillation signal OUT is outputted from the node N3. Owing to the electrical connection of the outside resistor R between the terminals 205 and 206 in such a circuit, a feedback circuit is made up of the outside resistor R and the internal capacitor 204. Thus, an oscillation output OUT having a frequency corresponding to the time constant T of these elements is obtained.
The operation of the CR oscillation circuit will next be described.
Now assume that a source voltage is represented as VDD, threshold voltages of respective inverters are respectively represented as 0.5VDD, and “H” and “L” of input and output levels are respectively represented as VDD and 0 (=GND) for simplification of description. Further, the input impedance of each inverter is assumed to be infinite.
When power is turned on at a time t0 in FIG. 2(B), the capacitor 204 is discharged and a voltage V21 at the node N1 is assumed to be 0. Since the voltage level of the node N1 is outputted to the node N2 via the inverters 201 and 202, a voltage V22 at the node N2 results in 0. Further, since the voltage V22 at the node N2 is inverted by the inverter 203, a voltage V23 at the node N3 becomes VDD.
With power-on at the time t0, the capacitor 204 starts to charge via the outside resistor R. Thus, the voltage V21 at the node N1 exponentially rises from 0 to VDD according to the time constant T of the capacitor 204 and the outside resistor R.
When the voltage V21 reaches 0.5VDD at a time t1, the voltage inputted to the inverter 201 exceeds the threshold voltage thereof. Thus, the voltage outputted from the inverter 201 reaches 0 and the voltage V2 on the output side of the inverter 202 changes from 0 to VDD. Since, at this time, the voltage charged in the capacitor 204 is 0.5VDD, the voltage V21 at the node N1 reaches 1.5VDD. On the other hand, the voltage V23 at the node N3 on the output side of the inverter 203 results in 0. Correspondingly, the voltage V21 at the node N1 exponentially decreases from 1.5VDD to 0 according to the time constant T.
When the voltage V21 decreases to 0.5VDD at a time t2, the input voltage of the inverter 201 reaches less than or equal to its threshold voltage. Consequently, the output voltage of the inverter 201 becomes VDD and the voltage V22 on the output side of the inverter 202 changes from VDD to 0. Since, at this time, the voltage charged in the capacitor 204 is 0.5VDD, the voltage V21 at the node N1 results in −0.5VDD. On the other hand, the voltage V23 at the node N3 on the output side of the inverter 203 reaches VDD. Correspondingly, the voltage V21 at the node N1 exponentially rises from −0.5VDD to VDD according to the time constant T.
When the voltage V21 increases to 0.5VDD at a time t3, the input voltage of the inverter 201 exceeds its threshold voltage. Consequently, the output voltage of the inverter 201 becomes 0 and the voltage V22 on the output side of the inverter 202 changes from 0 to VDD. Since, at this time, the voltage charged in the capacitor 204 is 0.5VDD, the voltage V21 at the node N1 results in 1.5VDD. On the other hand, the voltage V23 at the node N3 on the output side of the inverter 203 reaches 0. Correspondingly, the voltage V21 at the node N1 exponentially decreases from 1.5VDD to 0 according to the time constant T.
With similar repetitive operations, the respective inverters are subsequently periodically inverted according to the time constant T set by the values of the capacitor 204 and the resistor R, and an oscillation signal OUT having a desired frequency is outputted from the node N3.
However, the conventional CR oscillation circuit involves the following problems.
Although the outside resistor R having a value corresponding to an intended oscillation frequency is electrically connected to the terminals 205 and 206, such parasitic capacitance Cp as indicated by each dotted line in FIG. 2(A) is contained in an actually-connected outside resistor R. The parasitic capacitance Cp greatly varies according to the state of packaging thereof. Also a problem arises in that since the value of the built-in capacitor 204 is relatively small, the influence of each parasitic capacitance Cp increases, thus causing errors in a value at a single test on the outside resistor and an oscillation frequency at its packaging.